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FPGA Design

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  3. FPGA Design
FPGA Design

FPGA Design

FPGA development is an important part of the system design activity. Time-critical and logic-intensive designs are implemented in the FPGA to get a real-time response. FPGAs are extensively used for signal-processing applications. They are used along with a processor or in standalone mode. FPGAs are very flexible and the logic implemented can be reconfigured to meet the needs of the application.

What we have done:
  • Architectural Designing for signal processing applications using MATLAB (Simulink, System generator)
  • RTL Design & Coding and verifying at module level for RTL Sign Off. 
  • Design Synthesis and STA Using GENUS and Tempus tools
  • Serial Protocols UART, SPI and I2C.
  • High speed Serial Protocols like PCIe and Ethernet Protocol Controller IP 
  • DO-254 Safety Standard in develop and testing the safety critical systems
  • VHDL Assertion based test bench with safety critical standards
  • On-Chip High speed bus protocols - AHB, APB, AXI
  • Functional verification in compliance to standards. 
  • FPGA custom HW Board Bring-up. 
Interface and IP integrations:

InterfaceIP
Soft Processor Microblaze
Clock InputClocking wizard
DACAXI SPI
SensorsAXI IIC
TransceiversAXI UART
USBAXI USB2.0
Digital I/OAXI GPIO
LVDS / Differential SignalsBuffering
MemoryDDR3, LPDDR4 and DDR5
Booting MechanismsQSPI
InterfacesEthernet, SPI, I2C, UART, Backplane


FPGA Used:

Manufacturers: Xilinx, Altera, Lattice, and Actel,

Device Families: Xilinx Spartan3, Spartan 3A DSP, Virtex4, Virtex6 and ZYNQ 7000 Series, Altera Max5, Max10, ARRIA10, Agilex FPGAs, Lattice FPGA, Cyclone 10     GX, Artix - 7 

EDA Tools:

Xilinx (ISE, VIVADO), Altera Quartus Prime PRO, Lattice Diamond, Model SIM, SPY Glass (Linting, CDC), GENUS(Synthesis), Tempus (STA), Active HDL, Questa SIM, Xcelium (Cadence), SIM Vision

Hardware Descriptive Languages:

VHDL, Verilog HDL, System Verilog

Programming Languages:

C, Assembly Languages